A charge pump circuit is a circuit for generating a voltage higher than its input voltage. In some interface circuits, an output voltage higher than the input voltage and a large output current are required to be provided, thus a charge pump-type booster circuit, which can generate a large current output, is needed in the interface circuit chip. For example, in a Universal Serial Bus On-the-Go (USB OTG) interface circuit, a vbus in a cable is required to be driven to a voltage over 4.75V, and a current over 8 mA should be provided to a Self-Powered Device or a current higher than 100 mA should be provided to a Bus-Powered Device.
In A High-Efficiency CMOS Voltage Doubler, Pierre Favrat, et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 33, No. 3, MARCH 1998, a structure of a charge pump is described. FIG. 1 is a schematic diagram of the circuit structure of the charge pump, in which a clock signal CK changes periodically between an input voltage VIN and 0 and a CKN is the inverted clock of CK. After an operation time long enough, an output voltage VOUT will be finally stabilized at about 2×VIN. However, when a current with order of magnitude of tens or even hundreds mA is provided by using the charge pump shown in FIG. 1, the capacitance of the capacitor in the charge pump will be very large (with the order of magnitude of about 0.1 g), thereby causing that the capacitor only can be connected to the charge pump circuit in a chip pin mode from the outside of the charge pump circuit chip, thus one or more of nodes CP1 and CP2 will be pins for the chip to connect to the outside capacitor. In the practical application using standard CMOS manufacturing process, N-type metal oxide semiconductor (NMOS) N1a and N2a may be destroyed due to electrostatic discharge (ESD) or latchup, because their bulks have no independent wells for protection, and their sources or drains and their gates are connected to high voltage chip pins.
In A Regulated Charge Pump With Small Ripple Voltage and Fast Start-Up, Jae-Youl Lee, et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 41, NO. 2, FEBRUARY 2006, another structure of a charge pump is disclosed. FIG. 2 is a schematic diagram showing the circuit structure of the charge pump. There exist the following problems in the structure of this charge pump.
1) The drain and gate of a P-type metal oxide semiconductor (PMOS) P2b are connected with each other, which results in that, when a capacitor C2b is charged, the ascending extent of voltage on a node CP2 is limited, and the charges that can be obtained by the charge pump from the input voltage VIN in each period is limited. Therefore, such a structure greatly limits the quantity of charges that can be output from the node CP2 at a high potential (about 2×VIN). If providing a large current output by using such a structure, a chip with a large area is needed, and the cost is relatively high.
2) Because a bulk of an output switch P3b is connected with an output node VOUT, when other circuits connected with the VOUT requires to drive VOUT to logic 0 level when the charge pump is not at work, the PN junction between the P-type source (connected with the node CP2) and the N well (connected with the bulk) of the P3b will be forward conducting, thus the potential of VOUT can only be driven to VIN-VthPMOS-VthPN at the lowest (where VthPMOS is the cut-in voltage of the P-type metal oxide semiconductor, and VthPN is the forward conducting voltage of the PN junction), and cannot be normally driven to logic 0 level by the external circuit.
CN Patent NO. ZL 02157151.1 discloses a charge pump and a voltage doubler using the same. A schematic diagram of the whole circuit structure of the voltage doubler is as shown in FIG. 3, where CK and CKN are a pair of oscillation signals with opposite phases and a swing of 0˜VIN. The operating principle of the charge pump circuit is as follows.
It is hypothesized that, at the initial state, the potential of the node CKN is VIN and the potential of the node CK is 0, then a module 2 outputs a hclk1 (the initial potential of a signal hclk2 output by the module 2 is about VIN) signal with the potential of 0 to a module 1, so that the potential of the output signal CP1 of module 1 is pulled up to VIN via a switch P1c, while the potential of the output signal CP2 of module 1 is raised to VIN due to the capacitance characteristic. Then the potential of the node CKN is inverted to 0 and the potential of the node CK is inverted to VIN, and the potential of the output signal CP1 of module 1 is raised to 2×VIN due to the capacitance characteristic, the module 1 outputs the CP1 signal with the potential of 2×VIN to the module 2, the module 2 generates an hclk1 signal with a potential of 2×VIN by using the CP1 signal with the potential of 2×VIN output by the module 1 and outputs the hclk1 signal to the module 1, so that the CP1 signal output by the module 1 keeps at the potential of 2×VIN; furthermore, the module 2 further outputs an hclk2 signal with a potential of 0 to the module 1, so that the CP2 signal output by the module 1 is again raised to the potential of VIN (at the moment the potential of the node CKN is inverted to 0, the potential of the CP2 signal output by the module 1 is pulled down to 0 due to the capacitance characteristic). Subsequently, by the same token, when the potentials of the nodes CK and CKN are inverted between 0 and VIN, two output signals CP1 and CP2 with opposite phases may vary periodically in a range of VIN to 2×VIN.
The solution described in CN Patent NO. ZL 02157151.1 has the following disadvantages:
1) In addition to providing charges to the VOUT, the output signals CP1 and CP2 of the module 1 act as the input signals of the module 2 to make the potentials of the output signals hclk1 and hclk2 of the module 2 (at the same time, they are also the input signals of the module 1) change from 0 to 2×VIN and to make the potentials of the nodes a and b of the module 2 change from 0 to VIN, thus the charges stored by the capacitors C1c and C2c are wasted and the output charges are reduced;
2) When a circuit is required to output a large current (a current of tens or even hundreds mA) when the output voltage VOUT is higher than the input voltage VIN, the capacitance of the capacitor C1c or C2c would be of the order of magnitude of about 0.1 uF, thus the capacitor can only be connected from the outside of the circuit chip. At this point, the upper and lower plates of the capacitor and the VOUT are high voltage input/output pins of the chip. The metal oxide semiconductor would readily subject to the destruction of electrostatic discharge or latchup when the high voltage input/output pins (for example, CP1, CP2 and VOUT) of the chip are connected directly to the gate, the source and the drain of the metal oxide semiconductor (MOS) simultaneously;
3) Because the CK and CKN are an operation clock signal and an inverted operation clock signal with an opposite phase to the operation clock signal, respectively, the charge loss due to the clock level inversion cannot be avoided, and the efficiency of the energy output of the VOUT is relatively low. Especially, when the clock signal is inverted, a problem of charge loss may arise because a breakover current from the VIN to the GND may flow through a driver that provides charges to the lower plate of the capacitor C1c or C2c; and when the clock signal is inverted, a problem of charge loss may arise because the switches P6c and P5c and the switches P1c and P8c are conducting at the same time, which causes the charges to flow back from the CP1 (or CP2) with a high potential to the CP2 (or CP1) with a low potential. Furthermore, because the current that flows through each metal oxide semiconductor (MOS) is large in the application of outputting a large current, and the parasitic capacitance is relatively large due to the size of each MOS is relatively large, thus the ascending time and the descending time of the clock signal level inversion is relatively long, thereby causing the above two problems of charge loss to be serious. Moreover, because it is limited by the structural characteristic of this solution, even if the CK and CKN are modified as two-phase non-overlap clock signals, the above two problems of charge loss still cannot be solved at the same time.